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Author Archives: Niall Cooling
VSCode, Dev Containers and Docker: moving software development forward
Long term readers of this blog will know our devotion to using container-based technology, especially Docker, to significantly improve software quality through repeatable builds.
In the Autumn/fall of 2020, Microsoft introduced a Visual Studio Code (VSCode) extension Remote – Containers. With one quick stroke, this extension allows you to open a VSCode project within a Docker container.
Getting started with Dev Containers and Docker
There are several different approaches to using Dev Containers. In this post, we shall cover three options:
Using an existing […]
Posted in Agile, C/C++ Programming, Testing
Tagged C++, devcontainer, docker, GoogleMock, GoogleTest, Meson, ninja, VSCode
1 Comment
Introduction to the ARM® Cortex®-M7 Cache – Part 3 Optimising software to use cache
Part 1 Cache Basics
Part 2 Cache Replacement Policy
Caches – Why do we miss?
Cold Start
As stated, both data and instruction caches are required to be invalidated on system start. Therefore, the first load of any object (code or data) cannot be in cache (thus the cold start condition).
One available technique to help with cold-start conditions is the ability to pre-load data into the cache. The ARMv7-M instruction set adds the Preload Data (PLD) instruction. The PLD instruction signals to the memory […]
Introduction to the ARM® Cortex®-M7 Cache – Part 2 Cache Replacement Policy
Part 1 Cache Basics
Instruction Cache Replacement Policy
Starting with the simpler instruction cache case; when we encounter a cache miss the normal policy is to evict the current cache line and replace it with the new cache line. This is known as a read-allocate policy and is the default on all instruction caches.
Cold start (first read)
It should also be noted that on system power-up the initial state of the cache is unknown. On the ARMv7-M all caches are disabled at reset. […]
Introduction to the ARM® Cortex®-M7 Cache – Part 1 Cache Basics
For many years, the majority of smaller microprocessor-based systems have typically not used caches. With the launch of the ARMv7 architectures, caches were supported in the ARMv7-A family (e.g. Cortex-A8, etc.) but not supported in the core design of the ARMv7-M micro-controllers such as the Cortex-M3 and Cortex-M4. However, when the Cortex-M7 was announced, it broke that mould by offering cache support for the smaller embedded micro-controller.
This series is broken down in three parts:
Basic principles of cache
Cache replacement policies
Optimising software […]
Posted in ARM, CMSIS, Cortex, Design Issues
Tagged cache, Cortex-M, cortex-m7, modified harvard, TCM
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TDD with Compiler Explorer
Compiler Explorer (CE) has been around for several years now. When it first appeared on the scene, it immediately became an invaluable tool. Its ability to show generated assembler from given source code across many different compilers and ISAs (Instruction Set Architectures) is “mind-blowing”. We use it extensively when teaching as it allows you to clarify the effect your code can have on both performance and memory usage.
However, rather than limiting itself to only showing generated assembler, recent developments include the […]
Posted in Agile, C/C++ Programming, Testing
Tagged C++, C++11, Catch2, Compiler Explorer, doctest, GoogleTest, Modern C++, Testing
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Side effects and sequence points; why volatile matters
Introduction
Most embedded programmers, and indeed anyone who has attended a Feabhas programming course, is familiar with using the volatile directive when accessing registers. But it is not always obvious the ‘whys and wherefores’ of the use of volatile.
In this article, we explore why using volatile works, but more importantly, why it is needed in the first place.
Peripheral register access
If we start with a simple, fictitious, example. Suppose we have a peripheral with the following register layout:
register
width
offset
control
byte
0x00
configuration
byte
0x01
data
byte
0x02
status
byte
0x03
with a base address of […]
Posted in ARM, C/C++ Programming, CMSIS, Cortex
Tagged ARM, arm-gcc, sequence point, side effect, volatile
2 Comments
Running the eclipse-mosquitto MQTT Broker in a docker container
I first wrote about MQTT and IoT back in 2012, when I developed a simple C based library to publish and subscribe Quality of Service (QoS) level 0 MQTT messages.
Subsequently, MQTT has grown to be one of the most widely used IoT connectivity protocols with direct support from service such as AWS. Back in 2010, the first open-source MQTT Broker was Mosquitto. Mosquitto is now part of the Eclipse Foundation, and an iot.eclipse.org project, sponsored by cedalo.com.
Another area that has […]
Using a Raspberry Pi as a remote headless J-Link Server
Here at Feabhas we tend to favour using Segger J-Link’s as our ‘go-to’ solution for target flashing and debug, as they fall into that category of tools that just work.
As part of our ongoing work around Agile and CI (Continuous Integration), we’re always interested in addressing that challenging step of automating target based test in a cost-effective manner.
The Raspberry Pi (RPi) is a ubiquitous low-cost platform for numerous tasks. One useful tasks that it can be used for is as […]
Peripheral register access using C Struct’s – part 1
When working with peripherals, we need to be able to read and write to the device’s internal registers. How we achieve this in C depends on whether we’re working with memory-mapped IO or port-mapped IO. Port-mapped IO typically requires compiler/language extensions, whereas memory-mapped IO can be accommodated with the standard C syntax.
Embedded “Hello, World!”
We all know the embedded equivalent of the “Hello, world!” program is flashing the LED, so true to form I’m going to use that as an example.
The […]